Technology Gems Shine At Intel Developer Forum | CRN

The four days of the Intel Developer Forum in San Francisco saw some technology gems strewn in among the many high-profile platform announcements.

Among Intel’s expected preview of its new Core Microarchitecture were tidbits that promise significant enhancements to systems showing up next year. They included a flash memory addition to Intel’s next notebook platform, code-named Santa Rosa, which the company said will speed up boot time and save power; a plan to accelerate XML-based applications; and a research project intended to spur development of multithreaded software that can take advantage of processors with 10 to 100 cores.

Intel CTO Justin Rattner said Core Microarchitecture will deliver increased performance while reducing power requirements. It packs two processor cores with lower clock speeds onto one die while also improving cache and expanding internal pipes to move through more instructions simultaneously.

Solution providers have said Intel needs this new architecture to counter performance gains from rival Advanced Micro Devices. Though Intel’s performance claims can’t be verified until actual Core Microarchitecture systems are available, solution providers said the theory behind it is sound. But, several warned that not all software on the market today is multithreaded and will take full advantage of the benefits.

“It’s not a free lunch,” said Tau Leng, director of marketing at system builder Supermicro, San Jose, Calif. “Software also needs to support parallelism to get the kinds of performance benefits Intel is talking about.”

In the server space, Leng said the majority of applications, such as operating systems and databases, already support multithreading. But he warned that custom applications that sit on top of those products may not.

Intel said it has released software tools that make it easier for developers to recompile software to take advantage of multithreading capabilities. Intel’s first Core Microarchitecture products include a desktop CPU, code-named Conroe, in the third quarter. Merom, Intel’s chip for notebooks, will ship in the second half. Finally, server CPUs, code-named Woodcrest, will be delivered in the third quarter. Intel’s desktop and server platforms using the new chips this year will include its hardware-assisted virtualization technology and Advanced Management Technology, which will be the basis of a channel initiative for VARs and system builders that want to offer managed services to SMBs.

Further out, Intel said it will incorporate hardware-accelerated XML into future systems. Intel picked up the technology via its acquisition of Conformative, Austin, Texas. Intel believes the bulk of the Internet and many applications will be XML-based in the future.

“The theory is that XML traffic is rising rapidly and will dominate overall Web traffic over the next several years,” said Endpoint Technologies Associates analyst Roger Kay. “XML has a kind of predictable structure and if you could do something special to that process, you could have a better Web experience.”

Solution providers were particularly enthusiastic about Intel’s plan to build flash memory onto motherboards in its next notebook platform, expected to ship in 2007. Intel will use the flash memory to hold information necessary for boot-up. Executives said it will save power as well as time by requiring fewer hits to the hard drive.

“We need to have devices that boot very, very rapidly the same way that we get off the plane and immediately get a cell phone signal,” said Sean Maloney, executive vice president and general manager of Intel’s Mobility Group.

This is the kind of feature that mobile workers are expecting, said Jennifer Shine, vice president of marketing and business development at eMazzanti Technologies, a Hoboken, N.J., solution provider. “We are talking about people working on the go, and when you are in that mode you need to be able to open your laptop and go,” she said.

Intel, Santa Clara, Calif., also launched the TeraScale project to prepare for processors that will pack 10 to 100 cores on one die. Future products will need software that can handle multithreading but also catch potential conflicts as more cores compete to make use of chip memory, Rattner said.

The main problem centers around multiple threads trying to access the same memory location at the same time. Today’s method is to employ “locks” that manage the order of important data as it makes its way in and out of memory. Intel’s proposal adds what it calls transactional memory, which would recognize when a memory conflict arises in the multiple threads and would force all but one to try again.